Chemical mechanical polish (CMP) is a process that is used for the planarization of semiconductor wafers, particularly in gap-filling processes. CMP takes advantages of the synergetic effect of both physical and chemical forces for the polishing of wafers. It is performed by applying a load force to the back of a wafer while it rests on a pad. Both the pad and wafer are counter-rotated while a slurry, containing both abrasives and reactive chemicals, is passed underneath. CMP is an effective way to achieve truly global planarization over the entire substrate.
The existence of pattern effects in films polished by CMP processes is well known. There is a problem called a “micro-loading effect” that occurs due to a difference in pattern density, and it degrades the uniformity of pattern sizes. The “micro-loading effect” pertains to a phenomenon occurring upon simultaneously etching or polishing a pattern of a higher density and a pattern of a lower density; due to a difference in etching/polishing rate of a film from one location to another, the amount of reaction produced by the etching/polishing becomes locally dense or sparse, and convection of a large amount of reaction products by etching with a low volatility causes a non-uniformity in etching rate. Big variations in effective pattern density have been shown to result in significant and undesirable post-polish film thickness variation. Particularly, this non-uniformity causes a “dishing” effect on the surface of the circuit. “Dishing” means that a surface at a location with a lower pattern density was polished faster than the surface with a higher pattern density, hence forming a dish-shaped surface.
FIGS. 1 through 3 illustrate a conventional gap-filling process involving CMP. Referring to FIG. 1, polysilicon patterns 302 are formed over semiconductor substrate 300. Due to the non-uniformity in the pattern density, a pattern-dense region and a pattern-sparse region are formed. The pattern-dense region has a higher density and smaller spacing between polysilicon patterns 302 than the pattern-sparse region. In FIG. 2, inter-layer dielectric (ILD) 304 is deposited to fill the gaps between polysilicon patterns 302, and is deposited to a level higher than the top surface of polysilicon patterns 302. The topography of polysilicon patterns 302 is transferred partially to the top surface of ILD 304, which in turn has an uneven top surface. In addition, voids 306 may be generated, particularly in the pattern-dense region, in which the gaps have relatively high aspect ratios.
FIG. 3 illustrates the CMP for removing excess ILD 304. The CMP is carried out to remove the portion of ILD 304 over polysilicon patterns 302, until the top surfaces of polysilicon patterns 302 are exposed. The difference in the pattern densities between the pattern-dense region and the pattern-sparse region results in the non-uniformity in the CMP. For example, the topography in the top surface of ILD 304 has a lesser effect on the pattern-dense region than on the pattern-sparse region. As a result, dishing results in the pattern-sparse region, which dishing adversely affects the subsequent processes. On the other hand, the CMP may cause voids 306 to be exposed. In the subsequent processes, voids 306 may be undesirably filled with conductive materials, and may cause shorting of integrated circuits, or an increase in the RC delay.
Various methods have been explored to reduce or eliminate the micro-loading effect. For example, dummy patterns are created in the pattern-sparse region to increase the corresponding pattern density. However, the dummy patterns may adversely increase the RC delay. Further, there are regions unsuitable for forming dummy patterns. Accordingly, new gap-filling methods with reduced micro-loading effects are needed.